By Manho Lee, Jun So Pak, Joungho Kim
Through Silicon through (TSV) is a key know-how for knowing three-d built-in circuits (3D ICs) for destiny high-performance and low-power structures with small shape components. This ebook covers either qualitative and quantitative ways to provide insights of modeling TSV in a diverse viewpoints similar to sign integrity, strength integrity and thermal integrity. lots of the research during this booklet comprises simulations, numerical modelings and measurements for verification. the writer and co-authors in every one bankruptcy have studied deep into TSV for a few years and the gathered technical know-hows and information for comparable topics are comprehensively covered.
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Extra resources for Electrical Design of Through Silicon Via
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5. One of the bump-to-silicon substrate capacitances of the upper side of the silicon substrate, CBump1 , has to be added to CInsulator of the proposed equivalent circuit model, as shown in Fig. 7. This capacitance can be modeled as a parallelplate capacitor [19]. As shown in Fig. 7, the area, where the electric fields are formed, corresponds to where the bump overlies the silicon substrate through the inter-metal dielectric (IMD) layer. Thus, CBump1 is proportional to this area and inversely proportional to the IMD height, hIMD.
In order to measure the insertion loss through the TSV channel, TSVs are connected by stacking two dies. And the detailed dimensions are shown in Fig. 17c. There are two pairs of signal and ground TSVs on each side and each pair are connected each other by RDLs which are fabricated on the of the bottom die. For the S-parameter measurements, on-chip cascade probes and a vector network analyzer (VNA), the Agilent N2530A, are used. Measurement results are compared to those from the proposed equivalent circuit model of the fabricated test vehicle.
As a result, wide I/O design could be achieved more efficiently by using TSVs and the number of I/Os of a TSV-based 3D IC will keep increasing. Thus, understanding the electrical behavior of a TSV, which can greatly impact on the overall 3D IC system performance is very important. To design high-speed I/O channels with TSVs and perform signal integrity analysis for the advanced 3D IC design, the TSVs must be electrically modeled using design parameters such as geometric and material information up to the GHz range.