Download Design of Very High-Frequency Multirate Switched-Capacitor by Ben U Seng Pan, Rui Paulo da Silva Martins, Jose de PDF

By Ben U Seng Pan, Rui Paulo da Silva Martins, Jose de Albuquerque Epifanio da Franca

Design of Very High-Frequency Multirate Switched-Capacitor Circuits offers the idea and the corresponding CMOS implementation of the radical multirate sampled-data analog interpolation strategy which has its nice capability on very high-frequency analog frond-end filtering as a result of its inherent twin benefit of lowering the rate of data-converters and DSP middle including the specification leisure of the publish continuous-time filtering. this system thoroughly removes the conventional phenomenon of sampled-and-hold frequency-shaping on the decrease enter sampling expense. additionally, to be able to take on actual IC imperfections at very excessive frequency, the state of the art circuit layout and structure innovations for high-speed Switched-Capacitor (SC) circuits are comprehensively discussed:

-Optimum circuit structure tradeoff analysis
-Simple pace and gear trade-off research of energetic elements
-High-order filtering reaction accuracy with admire to capacitor-ratio mismatches
-Time-interleaved influence with admire to achieve and offset mismatch
-Time-interleaved influence with appreciate to timing-skew and random jitter with non-uniformly holding
-Stage noise research and allocation scheme
-Substrate and provide noise reduction
-Gain-and offset-compensation techniques
-High-bandwidth low-power amplifier layout and layout
-Very low timing-skew multiphase generation

Two tailored optimal layout examples in CMOS are offered. the 1st one achieves a 3-stage 8-fold SC interpolating clear out with 5.5MHz bandwidth and 108MHz output sampling expense for a NTSC/PAL CCIR 601 electronic video at three V. one other is a 15-tap 57MHz SC FIR bandpass interpolating clear out with 4-fold sampling price elevate to 320MHz and the first-time embedded frequency band up-translation for DDFS procedure at 2.5V. The corresponding chip prototype achieves thus far the top working frequency, optimum clear out order and maximum middle frequency with maximum dynamic variety lower than the bottom provide voltage in comparison to the formerly mentioned high-frequency SC filters in CMOS.

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Extra resources for Design of Very High-Frequency Multirate Switched-Capacitor Circuits: Extending the Boundaries of CMOS Analog Front-End Filtering

Example text

1983. Maloberti, “An optimum CMOS Switched-Capacitor antialiasing decimating filter,” IEEE J. 962-970, Sep. 1993. Mitra, “Multirate analog-digital systems for signal processing and conversion,” Proc. 1997. Martins, “IIR Switched-Capacitor decimator building blocks with optimum implementation,” IEEE Trans. Circuits and Systems, Vol. 81-90, Jan. 1990. Brisco, “CMOS analog front-end for conversational video phone modem,” in Proc. 4/5, 1989. Dallavalle, “PCM Telephony: Reduced architecture for a D/A converter and filter combination,” IEEE J.

Abidi, “A CMOS channel-select filter for a directconversion wireless receiver,” IEEE J. 722-729, May 1997. Franca, “A CMOS Switched-Capacitor bandpass filter with 100 MSample/s input sampling and frequency downconversion,” in Proc. European SolidState Circuits Conference (ESSCIRC), pp. 2000. 111-114, 2001. Copeland, “Biquad Alternative for High-Frequency SwitchedCapacitor Filters,” IEEE J. 1985. Conti, “High-frequency fully differential filter using operational amplifiers without common-mode feedback,” IEEE J.

30] approaches have been proposed. The former solution needs to involve the precise opamp gain value as a parameter into circuit capacitor sizing for compensating the finite gain effects, thus, not only requiring an additional gain-control-closed-loop circuitry, to accurately steady the opamp gain, but also significantly increasing the design complexity especially for higher-order filter transfer function. Meanwhile, the gain enhancement in the latter depends on the mismatch between main- and replica-amplifiers, and the circuit has poor common-mode rejection ratio (CMRR), which is increasingly important for high-frequency mixed signal ICs.

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